- Parallel to serial converter drivers#
- Parallel to serial converter driver#
- Parallel to serial converter series#
The parallel-to-serial converter as recited in claim 1, wherein the parallel-to-serial conversion unit comprises: a node terminated to a first level and a plurality of first drivers configured to drive the node to a second level in response to the plurality of input data and the clock signals used in the parallel-to-serial conversion unit, wherein the plurality of data are serially output in response to a logic level of the node.ġ0. The parallel-to-serial converter as recited in claim 1, further comprising a delay unit configured to delay the clock signals used in the parallel-to-serial conversion unit by a predetermined amount, thereby ensuring a margin between the output data by using output signals of the delay unit.ĩ. The parallel-to-serial converter as recited in claim 1, wherein the predetermined phase difference is adjusted to have a data width at which the output data of the parallel-to-serial converter are not overlapped.Ĩ.
Parallel to serial converter series#
The parallel-to-serial converter as recited in claim 5, wherein each of the first drivers comprises a first transistor configured to receive one of the plurality of valid data, and a second transistor connected in series to the first transistor and configured to receive one of the clock signals used in the parallel-to-serial conversion unit, and each of the second drivers comprises a third transistor configured to receive one of the inverted valid data, and a fourth transistor connected in series to the third transistor and configured to receive one of the clock signals used in the parallel-to-serial conversion unit.ħ.
Parallel to serial converter driver#
The parallel-to-serial converter as recited in claim 2, wherein the parallel-to-serial conversion unit comprises: a plurality of first drivers configured to drive a first node to a first level in response to the plurality of valid data and the clock signals used in the parallel-to-serial conversion unit a plurality of second drivers configured to drive a second node to a second level in response to inverted valid data and the clock signals used in the parallel-to-serial conversion units and a third driver configured to drive the first node and the second node to different logic levels in response to logic levels of the first node and the second node.Ħ.
The parallel-to-serial converter as recited in claim 3, wherein the plurality of parallel data input to the data input unit are input as the valid data through the data input unit, and are output as valid output data of the parallel-to-serial conversion unit during only a period where the data are selected as the valid data through the parallel-to-serial conversion unit.ĥ. The parallel-to-serial converter as recited in claim 2, wherein the parallel-to-serial conversion unit selects the plurality of data as valid data during enable periods of the clock signals used in the parallel-to-serial conversion unit.Ĥ.
The parallel-to-serial converter as recited in claim 1, wherein the data input unit receives the plurality of data as valid data during enable periods of the clock signals used in the data input unit.ģ. A parallel-to-serial converter, comprising: a data input unit having a plurality of input blocks configured to receive a plurality of parallel data by using a plurality of clock signals having different phases and a parallel-to-serial conversion unit having a plurality of first drivers configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals, wherein each of the plurality of clock signals inputted to the plurality of input blocks has a predetermined constant phase difference from each of the plurality of clock signals inputted to the plurality of first drivers corresponding to the plurality of input blocks.Ģ.